-- sdr.vhd


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity sdr is
	port (
		sdr_address       : in    std_logic_vector(24 downto 0) := (others => '0'); --   sdr.address
		sdr_byteenable_n  : in    std_logic_vector(0 downto 0)  := (others => '0'); --      .byteenable_n
		sdr_chipselect    : in    std_logic                     := '0';             --      .chipselect
		sdr_writedata     : in    std_logic_vector(7 downto 0)  := (others => '0'); --      .writedata
		sdr_read_n        : in    std_logic                     := '0';             --      .read_n
		sdr_write_n       : in    std_logic                     := '0';             --      .write_n
		sdr_readdata      : out   std_logic_vector(7 downto 0);                     --      .readdata
		sdr_readdatavalid : out   std_logic;                                        --      .readdatavalid
		sdr_waitrequest   : out   std_logic;                                        --      .waitrequest
		inout_ras_n       : out   std_logic;                                        -- inout.ras_n
		inout_dqm         : out   std_logic_vector(0 downto 0);                     --      .dqm
		inout_cs_n        : out   std_logic;                                        --      .cs_n
		inout_cas_n       : out   std_logic;                                        --      .cas_n
		inout_ba          : out   std_logic_vector(1 downto 0);                     --      .ba
		inout_addr        : out   std_logic_vector(12 downto 0);                    --      .addr
		inout_we_n        : out   std_logic;                                        --      .we_n
		inout_dq          : inout std_logic_vector(7 downto 0)  := (others => '0'); --      .dq
		inout_cke         : out   std_logic;                                        --      .cke
		clk_clk           : in    std_logic                     := '0';             --   clk.clk
		clk_1_reset_n     : in    std_logic                     := '0'              -- clk_1.reset_n
	);
end entity sdr;

architecture rtl of sdr is
	component sdr_sdram_0 is
		port (
			clk            : in    std_logic                     := 'X';             -- clk
			reset_n        : in    std_logic                     := 'X';             -- reset_n
			az_addr        : in    std_logic_vector(24 downto 0) := (others => 'X'); -- address
			az_be_n        : in    std_logic_vector(0 downto 0)  := (others => 'X'); -- byteenable_n
			az_cs          : in    std_logic                     := 'X';             -- chipselect
			az_data        : in    std_logic_vector(7 downto 0)  := (others => 'X'); -- writedata
			az_rd_n        : in    std_logic                     := 'X';             -- read_n
			az_wr_n        : in    std_logic                     := 'X';             -- write_n
			za_data        : out   std_logic_vector(7 downto 0);                     -- readdata
			za_valid       : out   std_logic;                                        -- readdatavalid
			za_waitrequest : out   std_logic;                                        -- waitrequest
			zs_addr        : out   std_logic_vector(12 downto 0);                    -- export
			zs_ba          : out   std_logic_vector(1 downto 0);                     -- export
			zs_cas_n       : out   std_logic;                                        -- export
			zs_cke         : out   std_logic;                                        -- export
			zs_cs_n        : out   std_logic;                                        -- export
			zs_dq          : inout std_logic_vector(7 downto 0)  := (others => 'X'); -- export
			zs_dqm         : out   std_logic_vector(0 downto 0);                     -- export
			zs_ras_n       : out   std_logic;                                        -- export
			zs_we_n        : out   std_logic                                         -- export
		);
	end component sdr_sdram_0;

	component sdr_rst_controller is
		port (
			reset_in0 : in  std_logic := 'X'; -- reset
			clk       : in  std_logic := 'X'; -- clk
			reset_out : out std_logic         -- reset
		);
	end component sdr_rst_controller;

	signal rst_controller_reset_out_reset           : std_logic; -- rst_controller:reset_out -> rst_controller_reset_out_reset:in
	signal clk_1_reset_n_ports_inv                  : std_logic; -- clk_1_reset_n:inv -> rst_controller:reset_in0
	signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> sdram_0:reset_n

begin

	sdram_0 : component sdr_sdram_0
		port map (
			clk            => clk_clk,                                  --   clk.clk
			reset_n        => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
			az_addr        => sdr_address,                              --    s1.address
			az_be_n        => sdr_byteenable_n,                         --      .byteenable_n
			az_cs          => sdr_chipselect,                           --      .chipselect
			az_data        => sdr_writedata,                            --      .writedata
			az_rd_n        => sdr_read_n,                               --      .read_n
			az_wr_n        => sdr_write_n,                              --      .write_n
			za_data        => sdr_readdata,                             --      .readdata
			za_valid       => sdr_readdatavalid,                        --      .readdatavalid
			za_waitrequest => sdr_waitrequest,                          --      .waitrequest
			zs_addr        => inout_addr,                               --  wire.export
			zs_ba          => inout_ba,                                 --      .export
			zs_cas_n       => inout_cas_n,                              --      .export
			zs_cke         => inout_cke,                                --      .export
			zs_cs_n        => inout_cs_n,                               --      .export
			zs_dq          => inout_dq,                                 --      .export
			zs_dqm         => inout_dqm,                                --      .export
			zs_ras_n       => inout_ras_n,                              --      .export
			zs_we_n        => inout_we_n                                --      .export
		);

	rst_controller : component sdr_rst_controller
		port map (
			reset_in0 => clk_1_reset_n_ports_inv,        -- reset_in0.reset
			clk       => clk_clk,                        --       clk.clk
			reset_out => rst_controller_reset_out_reset  -- reset_out.reset
		);

	clk_1_reset_n_ports_inv <= not clk_1_reset_n;

	rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;

end architecture rtl; -- of sdr
